Head-Separated Camera Device and Control Method Thereof

ABSTRACT

According to one embodiment, a method for controlling a head-separated camera device in which a camera head and a camera control unit are connected to each other by a cable comprising a line that supplies the camera head with serial data from the camera control unit. The method comprises outputting, by the camera control unit, serial data containing information for specifying a predetermined control target device of a plurality of control target devices to be controlled, where the plurality of control target devices are implemented within the camera head. The method further comprises identifying, by the camera head, the predetermined control target device specified by the serial data received, and supplying the predetermined control target device with an active select signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.12/708,447, now U.S. Pat. No. ______, which is based upon and claims thebenefit of priority from Japanese Patent Application No. 2009-131128,filed May 29, 2009, the entire contents of which are incorporated hereinby reference.

BACKGROUND

1. Field

One embodiment of the present invention relates to a head-separatedcamera device and a control method thereof in which a camera head and aCCU (camera control unit) for controlling the camera head are separatefrom each other.

2. Description of the Related Art

As is known well, a head-separated camera device as described above isconfigured such that, for example, a camera head and a CCU arerespectively constituted as separate members both connected mutuallythrough a camera cable which bundles plural signal lines. The camerahead comprises a solid-state imaging element such as a CMOS(complementary metal-oxide semiconductor) sensor. The CCU supplies adrive control signal to a solid-state imaging element of the camerahead, and obtains a video signal by performing a signal processing on anoutput from the solid-state imaging element.

Recently, modifications aiming for much higher function and performancehave been made to the head-separated camera device. Accordingly, typesand bit rates of signals which are transferred between the camera headand the CCU have been increasing greatly. The number of signal linesbundled in the camera cable has therefore increased and thickened thecamera cable itself, and the number of terminals provided on a connectorfor connecting the camera cable and the camera head has also increasedand resulted in that the connecter tends to have a larger size.

In general, head-separated camera devices are developed for the purposeof, for example, visually inspecting narrow areas where people cannotenter in, and camera heads thereof are demanded to be downsized as muchas possible. Therefore, thickening of a camera cable and upsizing of aconnector for connecting a camera cable are considered as factors whichhinder downsizing of camera heads, and hence involve a serious problemto be avoided.

Jpn. Pat. Appin. KOKAI Publication No. 10-254825 discloses a techniqueof reducing the number of terminals in a semiconductor integratedcircuit by common use of any communication terminal and any otherterminal (such as a reference voltage terminal) among three bus lines ina semiconductor integrated circuit which comprises communicationterminals for data communication and is equipped with a datacommunication function according to a three-line-type serial datatransfer scheme.

Jpn. Pat. Appin. KOKAI Publication No. 11-252438 discloses a techniqueof reducing the number of cables between a camera head unit and a maincamera unit by adopting a configuration as follows. A compositesynchronization signal and a control signal of the camera head unit aretransferred, multiplexed with each other, from the main camera unit tothe camera head unit. A composite synchronization signal, a statussignal of the camera head unit, and a video signal are transferred,multiplexed with each other, from the camera head unit to the maincamera unit.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

A general architecture that implements the various feature of theinvention will now be described with reference to the drawings. Thedrawings and the associated descriptions are provided to illustrateembodiments of the invention and not to limit the scope of theinvention.

FIG. 1 is a block configuration diagram representing an embodiment ofthe present invention, to describe an entire signal processing system ofa head-separated camera;

FIG. 2 is a block configuration diagram for describing an example of acamera head of the head-separated camera according to the embodiment;

FIG. 3 is a timing chart for describing control operation for controltarget devices in the camera head represented in FIG. 2, according tothe embodiment;

FIGS. 4A and 4B each are a timing chart for describing control operationfor control target devices by a DAC in the camera head represented inFIG. 2, according to the embodiment;

FIG. 5 is a block configuration diagram for describing an examplemodification to the camera head represented in FIG. 2, according to theembodiment;

FIG. 6 is a block configuration diagram for describing a signalprocessing system of a CCU connected to the camera head represented inFIG. 5, according to the embodiment;

FIG. 7 is a block configuration diagram for describing another exampleof a camera head in the head-separated camera according to theembodiment;

FIG. 8 is a timing chart for describing an example of control operationfor control target devices by a switcher in the camera head representedin FIG. 7, according to the embodiment;

FIG. 9 is a timing chart for describing another example of controloperation for control target devices by a switcher in the camera headrepresented in FIG. 7, according to the embodiment;

FIG. 10 is a timing chart for describing still another example ofcontrol operation for control target devices by a switcher in the camerahead represented in FIG. 7, according to the embodiment;

FIG. 11 is a block configuration diagram for describing a still anotherexample of the camera head in the head-separated camera according to theembodiment;

FIG. 12 is a diagram for describing data strings stored in a ROM in thecamera head represented in FIG. 11, according to the embodiment;

FIG. 13 is a diagram for describing details of a data string stored inthe ROM in the camera head represented in FIG. 11, according to theembodiment;

FIG. 14 is a flowchart for describing an example of control operationfor control target devices by a microcomputer in the camera headrepresented in FIG. 11, according to the embodiment;

FIG. 15 is a block configuration diagram for describing an examplemodification to the camera head represented in FIG. 11, according to theembodiment;

FIG. 16 is a block configuration diagram for describing an examplemodification to the head-separated camera according to the embodiment;

FIGS. 17A to 17C each are a timing chart for describing operation of thehead-separated camera represented in FIG. 16, according to theembodiment;

FIGS. 18A to 18C each are a timing chart for describing other operationof the head-separated camera represented in FIG. 16, according to theembodiment;

FIG. 19 is a block configuration diagram for describing an examplemodification to the camera head represented in FIG. 2, according to theembodiment; and

FIG. 20 is a flowchart for describing an example of a method in whichthe CCU detects presence or absence of connection to the camera head inthe head-separated camera according to the embodiment.

DETAILED DESCRIPTION

Various embodiments according to the invention will be describedhereinafter with reference to the accompanying drawings. In general,according to one embodiment of the invention, a camera control unitoutputs serial data containing information for specifying apredetermined control target device to be controlled from among pluralcontrol target devices comprised in a camera head. The camera headidentifies the control target device specified by the received serialdata, and supplies the identified control target device with a selectsignal for an active state.

FIG. 1 illustrates a total signal processing system of a head-separatedcamera described in this embodiment. That is, the head-separated camerais configured such that a camera head 11 and a CCU 12 which controls thecamera head 11 are connected to each other by a camera cable 13.

In this configuration, the camera head 11 comprises an imaging lens 14.An optical image of a subject which is let enter through the imaginglens 14 is formed on a light receiving surface of a solid-state imagingelement 15 which is constituted by, for example, a CMOS sensor. Based oncontrol from a drive control module 16, the solid-state imaging element15 converts the optical image formed on the light receiving surface intoa corresponding video signal, and outputs the video signal to a signalprocessing module 17.

The signal processing module 17 performs a predetermined signalprocessing such as a sample hold processing or avideo-synchronization-signal generation processing on the video signalinput, and thereafter supplies the video signal and the videosynchronization signal to an output terminal 18. The video signal andthe video synchronization signal supplied to the output terminal 18 arefurther supplied to an input terminal 20 of the CCU 12 described abovethrough a signal bus line 19 which constitutes part of the camera cable13.

The CCU 12 supplies a video-signal processing module 21 with the videosignal and the video synchronization signal both supplied to the inputterminal 20, and performs a preset predetermined signal processingthereon. Further, the video signal and the video synchronization signalboth output from the video signal processing module 21 are output to anunillustrated monitor through an output terminal 22, and are therebysubjected to video display.

The CCU 12 comprises a micro processing unit (MPU) 23. The MPU 23receives operation information of a user which is supplied from outsidethrough an input terminal 24. The MPU 23 controls the video signalprocessing module 21 so as to reflect the operation information,generates a control signal for the camera head 11, and supplies thecontrol signal to the control terminal 25.

The control signal supplied to the control terminal 25 is supplied to acontrol terminal 27 of the camera head 11 through a control signal busline 26 which also constitutes part of the camera cable 13. The camerahead 11 supplies the drive control module 16 with the control signalsupplied to the control terminal 27.

Based on the input control signal, the drive control module 16 generatesa drive control signal for controlling various processing operations ofthe solid-state imaging element 15, and supplies the drive controlsignal to the solid-state imaging element 15. The drive control module16 further comprises a memory module 28 for storing various settinginformation for the solid-state imaging element 15, and performs drivecontrol of the solid-state imaging element 15, using together theinformation in the memory module 28 upon necessity.

The drive control module 16 also comprises a communication module 29which performs information communication with the MPU 23 of the CCU 12.The drive control module 16 functions to receive a control signal fromthe MPU 23 through the communication module 29, and to transfer variousinformation (such as content stored in the memory module 28) in thecamera head 11 to the MPU 23, based on a request from the MPU 23.

Hence, this embodiment is configured to be capable of controlling thecamera head 11 without increasing the number of lines included in thecontrol signal bus line 29 constituting the camera cable 13, even if thenumber of various control target devices to be controlled, such as thesolid-state imaging element 15, drive control module 16, signalprocessing module 17, memory module 28, and communication module 29which constitute the camera head 11, increases to achieve high functionand performance for the camera head 11.

FIG. 2 represents an example of a case that the MPU 23 of the CCU 12controls six control target devices in accordance with thethree-line-type serial bus control scheme, for the camera head 11including six control target devices which are three CMOS sensors 30 a,30 b, and 30 c and three electrically-erasable-and-programmable readonly memories (EEPROM) 30 d, 30 e, and 30 f.

Each of the CMOS sensors 30 a to 30 c is provided with an input end fora reset signal RST, an input end for a chip select signal CS, an inputend for a serial clock SCLK, and an input end for serial input data SID.Also, each of the EEPROMs 30 d to 30 f is provided with an input end forthe chip select signal CS, an input end for the serial clock SCLK, aninput end for the serial input data SID, and an output end for serialoutput data SOD.

Further, the camera head 11 is provided with an input end 30 g for thechip select signal CS, an input end 30 h for the serial clock SCLK, aninput end 30 i for the serial input data SID, and an output end 30 j forthe serial output data SOD. These input ends 30 g to 30 i and the outputend 30 j each are connected to the MPU 23 of the CCU 12 through thecontrol signal bus line 26 constituting part of the camera cable 13, tomake information communicable therebetween.

Of these ends, the input end 30 g for the chip select signal CS, theinput end 30 h for the serial clock SCLK, and the input end 30 i for theserial input data SID are connected to a digital-to-analog converter(DAC) 30 k. The DAC 30 k comprises first to seventh output ends 1 to 7,and a reset signal RST common to the CMOS sensors 30 a to 30 c is outputfrom the first output end 1.

The DAC 30 k outputs a chip select signal CS to be supplied to the CMOSsensor 30 a from the second output end 2, a chip select signal CS to besupplied to the CMOS sensor 30 b from the third output end 3, as well asa chip select signal CS to be supplied to the CMOS sensor 30 c from thefourth output end 4.

Further, the DAC 30 k outputs a chip select signal CS to be supplied tothe EEPROM 30 d from the fifth output end 5, a chip select signal CS tobe supplied to the EEPROM 30 e from the sixth output end 6, as well as achip select signal CS to be supplied to the EEPROM 30 f from the seventhoutput end 7.

The serial clock SCLK supplied to the input end 30 h is supplied incommon to each of the CMOS sensors 30 a to 30 c and EEPROMs 30 d to 30 fthrough a gate module 301 which is controlled to open/close based on thechip select signal CS supplied to the input end 30 g. Further, theserial input data SID supplied to the input end 30 i is supplied incommon to each of the CMOS sensors 30 a to 30 c and EEPROMs 30 d to 30 fthrough a gate module 30 m which is also controlled to open/close basedon the chip select signal CS supplied to the input end 30 g.

The serial output data SOD from the EEPROM 30 d is derived from theoutput end 30 j through a gate module 30 n which is controlled toopen/close based on the chip select signal CS output from the fifthoutput end 5 of the DAC 30 k.

The serial output data SOD from the EEPROM 30 e is derived from theoutput end 30 j through a gate module 30 o which is controlled toopen/close based on the chip select signal CS output from the sixthoutput end 6 of the DAC 30 k.

The serial output data SOD from the EEPROM 30 f is derived from theoutput end 30 j through a gate module 30 p which is controlled toopen/close based on the chip select signal CS output from the seventhoutput end 7 of the DAC 30 k.

Each of the CMOS sensors 30 a to 30 c, EEPROMs 30 d to 30 f and DAC 30 kas described above is a control target device to be controlled, and isselected when the chip select signal CS is activated, i.e., invertedfrom a level H (high) to a level L (low), as represented in FIG. 3. Inthis state of being selected, input of the serial input data SID andoutput of the serial output data SOD from the EEPROMs 30 d to 30 f areperformed in synchronization with the serial clock SCLK.

In the camera head 11 represented in FIG. 2, operation of the MPU 23 ofcausing the CMOS sensor 30 c to input serial input data SID will bedescribed with reference to timing charts represented in FIGS. 4A and4B. That is, FIG. 4A represents a chip select signal CS, a serial clockSCLK, and serial input data SID which are input to the DAC 30 k. FIG. 4Brepresents a chip select signal CS, a serial clock SCLK, and serialinput data SID which are input to the CMOS sensor 30 c.

At first, as represented in FIG. 4A, the MPU 23 activates the chipselect signal CS (to the level L) which is input to the DAC 30 k at atime point T1. Then, the DAC 30 k is selected and inputs the serialinput data SID in synchronization with the serial clock SCLK which issupplied from the MPU 23. After inputting the serial input data SID tothe DAC 30 k, the MPU 23 inactivates the chip select signal CS (to thelevel H) input to the DAC 30 k.

In this case, a command for controlling the DAC 30 k to activate onlythe chip select signal CS (to the level L) supplied to the CMOS sensor30 s is written in the serial input data SID input to the DAC 30 k.Therefore, the DAC 30 k outputs a signal of the level L from the fourthoutput end 4 thereof at a time point T2, as represented in FIG. 4B. Thatis, only the chip select signal CS supplied to the CMOS sensor 30 c isactivated (to the level L), and the CMOS sensor 30 c is selected.

At this time, as represented in FIG. 4A, the MPU 23 has alreadyinactivated the chip select signal CS (to the level H), and the gatemodules 30 j and 30 m are therefore both open. Thus, in a state that theCMOS sensor 30 c is selected and the gate modules 30 j and 30 m are bothopen, the MPU 23 outputs the serial clock SCLK and the serial input dataSID.

Accordingly, as represented in FIG. 4B, the selected CMOS sensor 30 c isinput with the serial clock SCLK and the serial input data SID which areoutput from the MPU 23. The serial input data SID is input to the CMOSsensor 30 c in synchronization with the serial clock SCLK.

In this manner, input of the serial input data SID to the CMOS sensor 30c is completed, and the MPU 23 then activates the chip select signal CS(to the level L) input to the DAC 30 k again at a time point T3, asrepresented in FIG. 4A. Then, the DAC 30 k is selected and inputs theserial input data SID in synchronization with the serial clock SCLKsupplied from the MPU 23.

In this case, a command for controlling the DAC 30 k to inactivate thechip select signal CS supplied to the CMOS sensor 30 c (to the level H)is written in the serial input data SID input to the DAC 30 k.Therefore, the DAC 30 k outputs a signal of the level H from the fourthoutput end 4 at a time point T4, as represented in FIG. 4B. That is, thechip select signal CS supplied to the CMOS sensor 30 c is inactivated(to the level H), and the CMOS sensor 30 c is released from the selectedstate.

Input of serial input data SID and output of serial output data SOD withrespect to the other CMOS sensors 30 a and 30 b and the EEPROMs 30 d to30 f can be achieved with ease as the MPU 23 controls the DAC 30 k toselect a control target device in the same manner as described above.

However, the gate modules 30 n to 30 p which open/close output of theserial output data SOD from the EEPROMs 30 d to 30 f are open whencorresponding chip select signals CS output from the fifth to seventhoutput ends 5 to 7 of the DAC 30 k are active (at the level L),respectively.

According to the camera head 11 configured as represented in FIG. 2, theMPU 23 selects the DAC 30 k by a chip select signal CS so that which ofthe CMOS sensors 30 a to 30 c and EEPROMs 30 d to 30 f should beselected is specified by the serial input data SID. Therefore, even ifthe number of control target devices increases, the number of controlsignal lines for transferring the chip select signal CS need not beincreased. Accordingly, downsizing of the camera head 11 can beeffectively promoted.

The DAC 30 k can respond to whatever different input/output levels theCMOS sensors 30 a to 30 c and EEPROMs 30 d to 30 f as control targetdevices have. For example, each of the CMOS sensors 30 a to 30 c can besupplied with a level H of 2.5 V and each of the EEPROMs 30 d to 30 fcan be supplied with a level L of 3.3 V, in case where the CMOS sensors30 a to 30 c each have a level H of 2.5 V and a level L of 0 V and theEEPROMs 30 d to 30 f each have a level H of 3.3 V and a level L of 0 V.In this case, the DAC 30 k preferably has a level H of 3.3 V.

If plural control target devices have respectively different levels H, abuffer need be provided to convert levels of the input serial clock SCLKand the serial input data SID in correspondence with the levels H of therespective control target devices.

FIG. 5 represents an example modification to the camera head 11represented in FIG. 2. FIG. 5 will now be described denoting the samecomponents as those in FIG. 2 at the same reference symbols. The DAC 30k is provided with an eighth output end 8, and a preset direct currentlevel which is, for example, a level H (3.3 V) is output from an outputend 30 q to the CCU 12.

As represented in FIG. 6, the CCU 12 comprises: output ends 31 a, 31 b,and 31 c for respectively outputting a chip select signal CS, a serialclock SCLK, and serial input data SID from the MPU 23 to the camera head11; an input end 31 d for inputting the serial output data SOD outputfrom the camera head 11 to the MPU 23; and an input end 31 e forinputting the direct current level H output from the camera head 11.

The direct current level H input to the input end 31 e among theaforementioned ends is supplied to an analog-to-digital converter (ADC)31 f, and is then supplied to the MPU 23 after being converted intodigital data corresponding to the direct current level H. Further, theMPU 23 can measure a cable length of the camera cable 13 by determininghow much the direct current level H output from the DAC 30 k hasdecreased at the time when the direct current level H is input to theinput end 31 e. Naturally in this case, the more the direct currentlevel H decreases, the longer the cable length is.

That is, in case of a head-separated camera, the length of the cameracable 13 need be detected in order to manage a delay amount of datatransferred between the camera head 11 and the CCU 12. As the directcurrent level H output from the DAC 30 k in the side of the camera head11 is detected by the CCU 12, the length of the camera cable 13 can beeasily measured.

FIG. 7 represents another example of a case that in a camera head 11comprising three control target devices 32 a, 32 b, and 32 c, a MPU 23of a CCU 12 controls the three control target devices 32 a to 32 c inaccordance with the three-line-type serial bus control scheme.

Each of the control target devices 32 a to 32 c is provided with aninput end for a chip select signal CS, an input end for a serial clockSCLK, an input end for serial input data SID, and an output end forserial output data SOD.

Further, the camera head 11 is provided with an input end 32 d for thechip select signal CS, an input end 32 e for the serial clock SCLK, aninput end 32 f for the serial input data SID, and an output end 32 g forthe serial output data SOD. These input ends 32 d to 32 f and the outputend 32 g each are connected to the MPU 23 of the CCU 12 through acontrol signal bus line 26 constituting part of a camera cable 13, tomake information communicable therebetween.

These input ends 32 d to 32 f and the output end 32 g are connected toeach of the control target devices 32 a to 32 c through a switcher 33.That is, the chip select signal CS, serial clock SCLK, and serial inputdata SID which are respectively supplied to the input ends 32 d to 32 fare supplied to a decoder 33 a constituting part of the switcher 33.

The chip select signal CS, serial clock SCLK, and serial input data SIDwhich are supplied to the input ends 32 d to 32 f can be supplied to thecontrol target device 32 a, respectively through gate modules 33 b, 33c, and 33 d which are controlled to open/close based on an output of thedecoder 33 a.

Further, the chip select signal CS, serial clock SCLK, and serial inputdata SID which are supplied to the input ends 32 d to 32 f can also besupplied to the control target device 32 b, respectively through gatemodules 33 e, 33 f, and 33 g which are controlled to open/close based onthe output of the decoder 33 a.

Also, the chip select signal CS, serial clock SCLK, and serial inputdata SID which are supplied to the input ends 32 d to 32 f can besupplied to the control target device 32 c, respectively through gatemodules 33 h, 33 i, and 33 j which are controlled to open/close based onthe output of the decoder 33 a.

Further, the serial output data SOD from the control target device 32 ais derived from the output end 32 g through a gate module 33 k which iscontrolled to open/close based on the chip select signal CS output fromthe gate module 33 b.

The serial output data SOD from the control target device 32 b isderived from the output end 32 g through a gate module 331 which iscontrolled to open/close based on the chip select signal CS output fromthe gate module 33 e.

Further, the serial output data SOD from the control target device 32 cis derived from the output end 32 g through a gate module 33 m which iscontrolled to open/close based on the chip select signal CS output fromthe gate module 33 h.

Each of the control target devices 32 a to 32 c is selected when thechip select signal CS is activated, i.e., inverted from a level H to alevel L, as represented in FIG. 3. In this selected state, input of theserial input data SID and output of the serial output data SOD areperformed in synchronization with the serial clock SCLK.

In the camera head 11 configured as represented in FIG. 7, exampleoperation of the MPU 23 of inputting the serial input data SID to thecontrol target device 32 b will be described with reference to a timingchart represented in FIG. 8.

At first, the MPU 23 varies the serial input data SID at a time point T1with the chip select signal CS maintained in an inactive (level H)state. In this case, the serial input data SID is pulse width modulationdata in which a level-L period corresponding to 1.5 cycles of the serialclock SCLK is located at the head, and subsequently, data continuestaking a level-L period corresponding to 0.5 cycles of the serial clockSCLK as a logic value “0” as well as a level-L period corresponding to 1cycle of the serial clock SCLK as a logic value “1”.

In FIG. 8, the serial input data SID indicates a logic value “0010”after a level-L period corresponding to 1.5 cycles of the serial clockSCLK. The logic value “0010” specifies the control target device 32 b.

Meanwhile, the decoder 33 a which constitutes part of the switcher 33 ofthe camera head 11 recognizes the serial input data SID as a command forspecifying any of the control target devices 32 a to 32 c when theserial input data SID is varied with the chip select signal CSmaintained inactive (level H).

In this case, the serial input data SID is a command which specifies“0010”, i.e., the control target device 32 b. At this time, the decoder33 a controls each of the gate modules 33 e to 33 g to open so that thechip select signal CS, serial clock SCLK, and serial input data SIDsupplied respectively to the input ends 32 d to 32 f are supplied to thecontrol target device 32 b.

After thus controlling the gate modules 33 e to 33 g corresponding tothe control target device 32 b to open, the MPU 23 activates the chipselect signal CS (to the level L) at a time point T2, and outputs theserial clock SCLK and the serial input data SID synchronized with theserial clock SCLK. In this manner, the control target device 32 b isselected, and serial input data SID is input to the control targetdevice 32 b in synchronization with the serial clock SCLK.

The serial output data SOD from the control target device 32 b isderived from the output end 32 g through a gate module 331 which iscontrolled to open when the chip select signal CS output from the gatemodule 33 e is active (level L).

With respect to the other control target devices 32 a and 32 c, input ofserial input data SID and output of serial output data SOD can beperformed with ease as the MPU 23 controls the switcher 33 in the samemanner as described above.

According to the camera head 11 configured as represented in FIG. 7, theMPU 23 outputs a command for specifying any of the control targetdevices 32 a to 32 c by the serial input data SID when the chip selectsignal CS is inactive (level L). Further, the decoder 33 a recognizes,as a command, the serial input data SID which is supplied when the chipselect signal CS is inactive (level L). The decoder 33 a controls eachof the gate modules 33 b to 33 m so as to allow input of the chip selectsignal CS, serial clock SCLK, and serial input data SID, and output ofthe serial output data SOD with respect to only any of the controltarget devices 32 a to 32 c which is specified by the command.Therefore, even if the number of control target devices increases, thenumber of control signal lines for transferring the chip select signalCS need not be increased. Accordingly, downsizing of the camera head 11can be effectively promoted.

Meanwhile, if the control target devices 32 a to 32 c have respectivelydifferent levels H, each of the gate modules 33 b to 33 m can beequipped with a buffer function to convert levels of input/output datain correspondence with the levels H of the respective control targetdevices 32 a to 32 c, usefully as a configuration.

FIG. 9 represents another example in which the MPU 23 specifies thecontrol target device 32 b in the camera head 11 configured asrepresented in FIG. 7. That is, the MPU 23 varies the serial input dataSID at a time point T1, with the chip select signal CS maintained in aninactive (level H) state.

In this case, the serial input data SID has a data configuration asfollows. A start bit S1 corresponding to one cycle of the serial clockSCLK is located at the head. Subsequently, data continues taking alevel-L period corresponding to 1 cycle of the serial clock SCLK as alogic value “0” as well as a level-H period corresponding to 1 cycle ofthe serial clock SCLK as a logic value “1”. Finally, a stop bit S2corresponding to 1 cycle of the serial clock SCLK is located at thetail. In FIG. 9, data indicating a logic value “0010” is insertedbetween a start bit S and a stop bit S, and specifies the control targetdevice 32 b.

Meanwhile, the decoder 33 a recognizes that the control target device 32b is specified, based on the serial input data SID which has beensupplied when the chip select signal CS has been in an inactivate (levelH) state. The decoder 33 a then controls each of the gate modules 33 eto 33 g to open so that the chip select signal CS, serial clock SCLK,and serial input data SID supplied respectively to the input ends 32 dto 32 f are supplied to the control target device 32 b.

After thus controlling the gate modules 30 e to 33 g corresponding tothe control target device 32 b to open, the MPU 23 activates the chipselect signal CS (to the level L) at a time point T2, and outputs theserial clock SCLK and the serial input data SID synchronized with theserial clock SCLK. In this manner, the control target device 32 b isselected, and the serial input data SID is input in synchronization withthe serial clock SCLK.

Further, the serial output data SOD from the control target device 32 bis derived from the output end 32 g through a gate module 331 which iscontrolled to open when the chip select signal CS output from the gatemodule 33 e is activate (level L).

With respect to the other control target devices 32 a and 32 c, input ofserial input data SID and output of serial output data SOD can beachieved with ease as the MPU 23 controls the switcher 33 in the samemanner as described above.

FIG. 10 represents still another example in which a MPU 23 specifies thecontrol target device 32 b in the camera head 11 configured asrepresented in FIG. 7. That is, the MPU 23 outputs the serial clock SCLKat a time point T1, with the chip select signal CS maintained in aninactive (level H) state, and varies the serial input data SID insynchronization with the serial clock SCLK.

In this case, the serial input data SID has a data configuration inwhich data continues taking a level-L period corresponding to 1 cycle ofthe serial clock SCLK as a logic value “0” as well as a level-H periodcorresponding to 1 cycle of the serial clock SCLK as a logic value “1”.In FIG. 10, the serial input data SID indicates a logic value “0010”,and specifies the control target device 32 b.

Meanwhile, the decoder 33 a recognizes that the control target device 32b is specified, based on the serial input data SID which has beensupplied along with the serial clock SCLK when the chip select signal CShas been in an inactivate (level H) state. The decoder 33 a thencontrols each of the gate modules 33 e to 33 g to open so that the chipselect signal CS, serial clock SCLK, and serial input data SID suppliedrespectively to the input ends 32 d to 32 f are supplied to the controltarget device 32 b.

After thus controlling the gate modules 30 e to 33 g corresponding tothe control target device 32 b to open, the MPU 23 activates the chipselect signal CS (to the level L) at a time point T2, and outputs theserial clock SCLK and the serial input data SID synchronized with theserial clock SCLK. In this manner, the control target device 32 b isselected, and the serial input data SID is input in synchronization withthe serial clock SCLK.

Further, the serial output data SOD from the control target device 32 bis derived from the output end 32 g through the gate module 331 which iscontrolled to open when the chip select signal CS output from the gatemodule 33 e is inactivate (level L).

With respect to the other control target devices 32 a and 32 c, input ofserial input data SID and output of serial output data SOD can beachieved with ease as the MPU 23 controls the switcher 33 in the samemanner as described above.

FIG. 11 represents an example of a case that in a camera head 11comprising three CMOS sensors 34 a, 34 b, and 34 c as control targetdevices, a MPU 23 of a CCU 12 controls the three control target devicesin accordance with a two-line serial bus control scheme.

Each of the CMOS sensors 34 a to 34 c is provided with an input end fora reset signal RST, an input end for a chip select signal CS, an inputend for a serial clock SCLK, and an input end for serial input data SID.

Among these ends, the input ends of the CMOS sensors 34 a to 34 c forthe chip select signal CS are connected to a microcomputer 34 grespectively through individual signal lines 34 d, 34 e, and 34 f.

The input ends for the reset signal RST, serial clock SCLK, and serialinput data SID for the reset signal RST in each of the CMOS sensors 34 ato 34 c are connected to the microcomputer 34 g respectively throughcommon signal lines 34 h, 34 i, and 34 j.

The microcomputer 34 g is connected to a ROM 341 through a parallel bus34 k. Further, the ROM 341 performs data writing/reading, based oncontrol from the microcomputer 34 g.

The camera head 11 is provided with: an input end 34 m which receivesdata output from the MPU 23 of the CCU 12 and supplies the data to themicrocomputer 34 g; and an output end 34 n which outputs data to betransferred from the microcomputer 34 g to the MPU 23. The input end 34m and the output end 34 n each are connected to the MPU 23 of the CCU 12through a control signal bus line 26 which constitutes part of a cameracable 13, to make information communicable.

As represented in FIG. 12, the ROM 341 stores data strings correspondingto various commands 1, 2, . . . , n which are output from the MPU 23 tothe microcomputer 34 g. For example, a data string corresponding to thecommand 1 consists of plural data items 1A, 1B, . . . , and an end code.A data string corresponding to the command 2 consists of plural dataitems 2A, 2B, . . . , and an end code. A data string corresponding tothe command n consists of plural data items nA, nB, . . . , and an endcode.

Of these data items, the data item 1A consists of a deviceidentification (ID) for specifying a control target device, and maindata, as represented in FIG. 13. The other data items 1B, . . . , 2A,2B, . . . , nA, nB, . . . , are configured in the same manner as in thedata item 1A. The device ID consists of, for example, 4 bits. “0000”specifies the CMOS sensor 34 a. “0001” specifies the CMOS sensor 34 b.“0010” specifies the CMOS sensor 34 c.

In the camera head 11 configured as represented in FIG. 11, exampleoperation of the MPU 23 of specifying and causing any of the CMOSsensors 34 a to 34 c to input serial input data SID will now bedescribed below with reference to a flowchart represented in FIG. 14.

This operation is started when the power supply of the camera head 11 ispowered on (step S1). Then, the microcomputer 34 g performs a presetinitialization processing in a step S2, and thereafter determineswhether a command has been received from the MPU 23 by the input end 34m or not in a step S3.

If a command is determined to have been received (YES), themicrocomputer 34 g analyzes the received command in a step S4, andreads, from the ROM 341, any one of data items contained in a datastring corresponding to the command in a step S5. Thereafter, themicrocomputer 34 g determines whether the read data item is an end codeor not in a step S6.

If the read data item is not determined to be an end code (NO), themicrocomputer 34 g identifies the device ID of the read data item in astep S7. If the device ID specifies the CMOS sensor 34 a, themicrocomputer 34 g activates the chip select signal CS supplied to theCMOS sensor 34 a (to the level L) in a step S8, and outputs main data ofthe read data item as serial input data SID. In this manner, input ofthe main data to the specified CMOS sensor 34 a is completed.Thereafter, the microcomputer 34 g is returned to the processing of thestep S5, and performs reading of a next data item.

Alternatively, if the device ID specifies the CMOS sensor 34 b in thestep S7, the microcomputer 34 g activates the chip select signal CSsupplied to the CMOS sensor 34 b (to the level L) in a step S9, andoutputs main data of the read data item as serial input data SID. Inthis manner, input of the main data to the specified CMOS sensor 34 b iscompleted. Thereafter, the microcomputer 34 g is returned to theprocessing of the step S5, and performs reading of a next data item.

Still alternatively, if the device ID specifies the CMOS sensor 34 c inthe step S7, the microcomputer 34 g activates the chip select signal CSsupplied to the CMOS sensor 34 c (to the level L) in a step S10, andoutputs main data of the read data item as serial input data SID. Inthis manner, input of the main data to the specified CMOS sensor 34 c iscompleted. Thereafter, the microcomputer 34 g is returned to theprocessing of the step S5, and performs reading of a next data item.

Otherwise, if the read data item is determined to be an end code (YES)in the step S6, the microcomputer 34 g generates response data to theMPU 23 in a step S11, and transmits the response data to the MPU 23through the output end 34 n in a step S12. The MPU 23 is then returnedto the processing of the step S3.

By receiving the response data, the MPU 23 completes the processing forthe microcomputer 34 g of the camera head 11, and can thereby detectitself in a state capable of receiving a next command. This responsedata also consists of a device ID, which specifies the MPU 23, and maindata as represented in FIG. 13.

The camera head 11 configured as represented in FIG. 11 comprises themicrocomputer 34 g which receives various commands output from the MPU23, and the ROM 341 which stores data strings corresponding to thevarious commands. Further, the microcomputer 34 g reads a data stringfrom the ROM 341, corresponding to a command from the MPU 23, andperforms control in a manner that serial input data SID is input to anyof the CMOS sensors 34 a to 34 c specified by the data string.Therefore, even if the number of control target devices increases, thenumber of control signal lines for transferring the chip select signalCS need not be increased. Accordingly, downsizing of the camera head 11can be effectively promoted.

Each of the data strings corresponding to commands contains a device ID,which specifies any of the CMOS sensors 34 a to 34 c respectively ascontrol target devices to be controlled, and main data to be supplied tothe control target device specified by the device ID. It is thereforeconvenient that an instruction to input main data can be given to eachof the plurality of control target devices by simply outputting onecommand from the MPU 23.

For example, if a command 1 is to set a gain for each of the CMOSsensors 34 a to 34 c, gain differences which are actually obtainedrelative to externally set gains are stored as data 1A, 1B, and 1C forthe CMOS sensors 34 a to 34 c, respectively. Specifically, if there isno difference between an externally set gain and an actually obtainedgain for the CMOS sensor 34 a, 0 is stored as the data 1A.

If an actually obtained gain is higher by +0.1 dB than an externally setgain for the CMOS sensor 34 b, −0.1 is stored as the data 1B. Further,if an actually obtained gain is lower by −0.1 dB than an externally setgain for the CMOS sensor 34 c, +0.1 is stored as the data 1C.

In this manner, if a command 1 which requests the gain of each of theCMOS sensors 34 a to 34 c to be set to 6 dB is output from the MPU 23,the microcomputer 34 g which receives the command 1 sets the gain of theCMOS sensor 34 a to 6 dB, based on the value “0” stored as the data 1A.

Further, the microcomputer 34 g sets the gain of the CMOS sensor 34 b to5.9 dB, based on the value “−0.1” stored as the data 1B. Themicrocomputer 34 g still sets the gain of the CMOS sensor 34 c to 6.1dB, based on the value “+0.1” stored as the data 1C.

That is, a processing of substantially aligning the gains of the CMOSsensors 34 a to 34 c with 6 dB is performed by only using the command 1which requests the gain of each of the CMOS sensors 34 a to 34 c to beset to 6 dB. Specifically, it is very effective that commandscorresponding in number to plural control target devices need not betransmitted from the CCU 12 to the camera head 11, even in response to arequest for changing settings of the plural control target devices allat once.

FIG. 15 represents an example modification to the camera head 11configured as represented in FIG. 11. FIG. 15 will now be describeddenoting the same components as those in FIG. 11 at the same referencesymbols. The output end 34 n for outputting data from the microcomputer34 g to the MPU 23 is removed. That is, a system in which themicrocomputer 34 g does not reply with any data to the MPU 23, i.e., asystem which performs one-way information communication from the MPU 23to the microcomputer 34 g may be configured as represented in FIG. 15.

FIG. 16 represents still another example modification to the camera head11 configured as represented in FIG. 11. That is, the control signal busline 26 connecting the camera head 11 and the CCU 12 is constituted byone control signal line 26 a capable of performing bidirectionalinformation communication. The CCU 12 comprises an input/output end 35 aconnected to the control signal line 26 a.

Further, data input through the input/output end 35 a is suppliedthrough the buffer 35 b to the MPU 23. Data output from the MPU 23 tothe microcomputer 34 g of the camera head 11 is supplied to a controlelectrode of a switching element 35 c whose control target electrode tobe controlled is connected to the input/output end 35 a. Further, theinput/output end 35 a is connected through a resistor 35 d to a powersupply terminal 35 e applied with a direct current voltage +B. In thismanner, the data output from the MPU 23 to the microcomputer 34 g of thecamera head 11 is transferred, inverted, by the control signal line 26a.

The camera head 11 is provided with an input/output end 35 f connectedto the control signal line 26 a. Data input through the input/output end35 f is supplied to the microcomputer 34 g through the buffer 35 g. Dataoutput from the microcomputer 34 g to the MPU 23 of the CCU 12 issupplied to a control electrode of a switching element 35 h whosecontrol target electrode to be controlled is connected to theinput/output end 35 f. In this manner, the data output from themicrocomputer 34 g to the MPU 23 of the CCU 12 is transferred, inverted,by the control signal line 26 a.

FIG. 17A represents data supplied from the MPU 23 to the controlelectrode of the switching element 35 c. The data output from the MPU 23is configured to contain a start code at the head, which is followed bymain data. FIG. 17B represents data supplied from the microcomputer 34 gto the control electrode of the switching element 35 h. This data isalso configured to contain a start code at the head which is followed bymain data. FIG. 17C represents data transferred by the control signalline 26 a.

As represented in FIG. 17C, when the MPU 23 and the microcomputer 34 galternately communicate data between each other, data output from theMPU 23 is transferred, inverted, on the control signal line 26 a. Also,data output from the microcomputer 34 g is transferred, inverted, on thecontrol signal line 26 a.

According to the camera head 11 represented in FIG. 16, datacommunication between the MPU 23 and the microcomputer 34 g can beperformed by only one control signal line 26 a. Therefore, even if thenumber of control target devices increases, the number of control signallines for transferring the chip select signal CS need not be increased.Accordingly, downsizing of the camera head 11 can be effectivelypromoted.

Meanwhile, if data output from the MPU 23 as represented in FIG. 18A anddata output from the microcomputer 34 g as represented in FIG. 18B areconcurrent on the control signal line 26 a, data on the control signalline 26 a is expressed as an inverted logical sum of both data asrepresented in FIG. 18C.

Therefore, through the buffer 35 b, the MPU 23 receives data which theMPU 23 itself has output to the switching element 35 c. If the outputdata and the data thus received are not accurate inversions of eachother, concurrence with output data from the microcomputer 34 g isdetected to occur.

Similarly, through the buffer 35 b, the microcomputer 34 g receives datawhich the microcomputer 34 g itself has output to the switching element35 h. If the output data and the data thus received are not accurateinversions of each other, concurrence with output data from the MPU 23is detected to occur.

FIG. 19 represents an example modification to the camera head 11represented previously in FIG. 2. FIG. 19 will now be described denotingthe same components as those in FIG. 2 at the same reference symbols. Aninput/output (I/O) expander 36 is used in place of the DAC 30 k.

That is, the input end 30 g for the chip select signal CS, the input end30 h for the serial clock SCLK, and the input end 30 i for the serialinput data SID are connected to the I/O expander 36. The I/O expander 36comprises first to seventh output ends 1 to 7. A reset signal RST to besupplied in common to the CMOS sensors 30 a to 30 c is output from thefirst output end 1.

The I/O expander 36 outputs a chip select signal CS supplied to the CMOSsensor 30 a from the second output end 2, a chip select signal CSsupplied to the CMOS sensor 30 b from the third output end 3, as well asa chip select signal CS supplied to the CMOS sensor 30 c from the fourthoutput end 4.

Further, the I/O expander 36 outputs a chip select signal CS supplied tothe EEPROM 30 d and the gate module 30 n from the fifth output end 5, achip select signal CS supplied to the EEPROM 30 e and the gate module 30o from the sixth output end 6, as well as a chip select signal CSsupplied to the EEPROM 30 f and the gate module 30 p from the seventhoutput end 7.

The I/O expander 36 is selected as the MPU 23 activates the chip selectsignal CS (to the level L) as well. Thereafter, the I/O expander 36activates an output end (to the level L) specified by serial input dataSID supplied from the MPU 23, thereby to select a control target deviceto be controlled.

Thereafter, operation of supplying a selected control target device witha serial clock SCLK and serial input data SID, operation of outputtingserial output data SOD from the selected control target device, andoperation of the MPU 23 of selecting the I/O expander 36 again andreleasing the selected control target device when input/output of serialdata ends are carried out in the same manner as described with respectto the DAC 30 k follows.

The I/O expander 36 outputs only one type of level H and cannot outputplural types of levels H. For example, there may be supposed a casewhere the I/O expander 36 has a level H of 2.5 V and a level L of 0 V,each of the CMOS sensors 30 a to 30 c has a level H of 2.5 V and a levelL of 0 V, as well as each of the EEPROMs 30 d to 30 f has a level H of3.3 V and a level L of 0 V. In this case, although the I/O expander 36can output directly the level H of 2.5 V to each of the CMOS sensors 30a to 30 c, each of the EEPROMs 30 d to 30 f need be supplied with alevel H of 3.3 V through a buffer for converting levels.

If plural control target devices have respectively different levels H, abuffer need be provided to convert levels of the input serial clock SCLKand serial input data SID in correspondence with the levels H of therespective control target devices.

Next, processing operation of the CCU 12 of detecting connection of thecamera head 11 represented in FIG. 1 will now be described withreference to a flowchart in FIG. 20. This operation is started bypowering on the power supply of the CCU 12 (in a step S13). Then, theMPU 23 accesses the drive control module 16 of the camera head 11through the control signal bus line 26 in a step S14 to determinewhether an initial state thereof is proper or not.

If the initial state of the drive control module 16 is determined to beproper (YES), the MPU 23 determines whether various settings areproperly complete for the solid-state imaging element 15 or not in astep S15. If settings are determined to be properly complete (YES), theMPU 23 determines whether a video synchronization signal has beendetected through a signal bus line 19 from the camera head 11 or not ina step S16.

If a video synchronization signal is determined to have been detected(YES), the MPU 23 determines the camera head 11 to be connectedproperly, in a step S17, and is then returned to the processing of thestep S16.

Alternatively, if the initial state of the drive control module 16 isnot determined to be proper (NO) in the step S14, if various settingsare not determined to be properly complete (NO) in the step S15, or ifany video synchronization signal is not determined to have been detected(NO) in the step S16, the MPU 23 does not determine the camera head 11to be properly connected in a step S17, and is returned to theprocessing of the step S14.

According to the connection detection method for the camera head 11 asdescribed above, far more accurate detection can be achieved comparedwith a method of detecting only whether a video synchronization signalhas been obtained from the camera head 11 or not, as in prior art.

The various modules of the systems described herein can be implementedas software applications, hardware and/or software modules, orcomponents on one or more computers, such as servers. While the variousmodules are illustrated separately, they may share some or all of thesame underlying logic or code.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the inventions. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the inventions. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the inventions.

1. A head-separated camera device comprising: a camera control unit; acamera head; and a cable comprising a line that supplies the camera headwith serial data from the camera control unit and connects the camerahead and the camera control unit to each other, wherein the cameracontrol unit is configured to output serial data containing informationfor specifying a predetermined control target device of a plurality ofcontrol target devices to be controlled, and the camera head comprises aconversion module that is configured to (i) identify the predeterminedcontrol target device specified by the serial data received and (ii)supply an active select signal to the identified predetermined controltarget device, the conversion module including a digital-to-analogconverter capable of outputting the active select signal at a pluralityof levels corresponding to input/output levels of the plurality ofcontrol target devices.
 2. The head-separated camera device of claim 1,wherein the conversion module being configured to identify thepredetermined control target device specified by the serial datareceived together with a second select signal, and to supply theidentified predetermined control target device with the active selectsignal.
 3. The head-separated camera device of claim 1, wherein thedigital-to-analog converter is configured to output a preset constantdirect current level to the camera control unit through the cable. 4.The head-separated camera device of claim 3, wherein the camera controlunit is configured to measure a length of the cable, based on a decreaseamount of the direct current level output from the digital-to-analogconverter.
 5. The head-separated camera device of claim 1, wherein thecable comprises a line that supplies the camera head with a selectsignal from the camera control unit.
 6. The head-separated camera deviceof claim 5, wherein the camera control unit is configured to output (i)an inactive select signal to the camera head, and (ii) the serial datacontaining information for specifying the predetermined control targetdevice in the camera head.
 7. A method for a head-separated cameradevice in which a camera head and a camera control unit are connected toeach other by a cable comprising a line that supplies the camera headwith serial data from the camera control unit, the method comprising:outputting, by the camera control unit, serial data containinginformation for specifying a predetermined control target device of aplurality of control target devices to be controlled, the plurality ofcontrol target devices being implemented within the camera head;identifying, by the camera head, the predetermined control target devicespecified by the serial data received; and supplying, by the camerahead, the predetermined control target device with an active selectsignal.
 8. The method of claim 7, wherein the supplying of the activeselect signal to the identified predetermined control target device isperformed by a digital-to-analog converter within the camera head. 9.The method of claim 8, wherein the digital-to-analog converter outputsthe active select signal at a level corresponding to an input/outputlevel of the predetermined control target device.
 10. The method ofclaim 8, wherein the digital-to-analog converter outputs the activeselect signal at different levels, each level corresponding to aninput/output level of the predetermined control target device of theplurality of control target devices.
 11. The method of claim 8 furthercomprising outputting, by the digital-to-analog converter, a presetconstant direct current level to the camera control unit through thecable.
 12. The method of claim 11 further comprising measuring, by thecamera control unit, a length of the cable, based on a decrease amountof the direct current level output from the digital-to-analog converter.13. The method of claim 7, wherein the outputting of the serial data bythe camera control unit further comprises outputting an inactive selectsignal to the camera head.
 14. A head-separated camera devicecomprising: a camera control unit; a camera head; and a cable comprisinga line that supplies the camera head with serial data from the cameracontrol unit and connects the camera head and the camera control unit toeach other, wherein the camera control unit is configured to outputserial data containing information for specifying a predeterminedcontrol target device of a plurality of control target devices to becontrolled, and the camera head comprises a digital-to-analog converterto (i) identify the predetermined control target device specified by theserial data received and (ii) supply an active select signal to theidentified predetermined control target device, the active select signalbeing set to one at a plurality of levels corresponding to aninput/output level of the predetermined control target device, each ofthe plurality of control target devices having a different input/outputlevel.
 15. The head-separated camera device of claim 14, wherein thedigital-to-analog converter to identify the predetermined control targetdevice using by the serial data and a select signal supplied by thecamera control unit.
 16. The head-separated camera device of claim 14,wherein the digital-to-analog converter is configured to output a presetconstant direct current level to the camera control unit through thecable.
 17. The head-separated camera device of claim 16, wherein thecamera control unit is configured to measure a length of the cable,based on a decrease amount of the direct current level output from thedigital-to-analog converter.
 18. The head-separated camera device ofclaim 14, wherein the cable comprises a line that supplies the camerahead with a select signal from the camera control unit, the selectsignal being used to identify the predetermined control target device.19. The head-separated camera device of claim 18, wherein the cameracontrol unit is configured to output (i) an inactive select signal tothe camera head, and (ii) the serial data containing information forspecifying the predetermined control target device in the camera head.